PIC18F2450/4450
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
13.4.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
3. Make the CCP1 pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
EQUATION 13-3:
FOSC
⎛
⎝
⎞
⎠
5. Configure the CCP module for PWM operation.
---------------
log
FPWM
PWM Resolution (max)
= ----------------------------- b i t s
log(2)
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 13-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
TABLE 13-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
—
TMR0IF
PD
INT0IF
POR
RBIF
BOR
49
50
51
51
51
51
50
50
50
50
50
50
IPEN
—
SBOREN(1)
ADIF
—
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
CCP1IF
CCP1IE
CCP1IP
TRISC2
TMR2IF
TMR2IE
TMR2IP
TRISC1
TMR1IF
TMR1IE
TMR1IP
TRISC0
PIE1
—
ADIE
—
IPR1
—
ADIP
—
TRISC
TMR2
PR2
TRISC7
TRISC6
—
Timer2 Register
Timer2 Period Register
T2CON
CCPR1L
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Capture/Compare/PWM Register 1 Low Byte
CCPR1H Capture/Compare/PWM Register 1 High Byte
CCP1CON DC1B1 DC1B0
—
—
CCP1M3 CCP1M2 CCP1M1 CCP1M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
DS39760A-page 128
Advance Information
© 2006 Microchip Technology Inc.
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