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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
The second timer is the Oscillator Start-up Timer  
(OST), intended to keep the chip in Reset until the  
crystal oscillator is stable (HS modes). The OST does  
this by counting 1024 oscillator cycles before allowing  
the oscillator to clock the device.  
3.8  
Power-up Delays  
Power-up delays are controlled by two timers, so that  
no external Reset circuitry is required for most applica-  
tions. The delays ensure that the device is kept in  
Reset until the device power supply is stable under nor-  
mal circumstances and the primary clock is operating  
and stable. For additional information on power-up  
delays, see Section 5.6 “Power-up Timer (PWRT)”.  
There is a delay of interval, TCSD (parameter 38,  
Table 24-10), following POR, while the controller  
becomes ready to execute instructions.  
The first timer is the Power-up Timer (PWRT), which  
provides a fixed delay on power-up (parameter 33,  
Table 24-10). It is always enabled.  
TABLE 3-3:  
OSC1 AND OSC2 PIN STATES IN SLEEP MODE  
Oscillator Mode  
OSC1 Pin  
OSC2 Pin  
EC, ECPLL  
HS, HSPLL  
Floating, pulled by external clock  
At logic low (clock/4 output)  
Feedback inverter disabled at quiescent  
voltage level  
Feedback inverter disabled at quiescent  
voltage level  
Note:  
See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.  
© 2009 Microchip Technology Inc.  
DS39682E-page 33  
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