欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第27页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第28页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第29页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第30页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第32页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第33页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第34页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第35页  
PIC18F45J10 FAMILY  
FIGURE 3-4:  
PLL BLOCK DIAGRAM  
3.4  
PLL Frequency Multiplier  
A Phase Locked Loop (PLL) circuit is provided as an  
option for users who want to use a lower frequency  
oscillator circuit, or to clock the device up to its highest  
rated frequency from a crystal oscillator. This may be  
useful for customers who are concerned with EMI due  
to high-frequency crystals, or users who require higher  
clock speeds from an internal oscillator. For these  
reasons, the HSPLL and ECPLL modes are available.  
HSPLL or ECPLL (CONFIG2L)  
PLL Enable (OSCTUNE)  
OSC2  
Phase  
Comparator  
FIN  
HS or EC  
OSC1 Mode  
FOUT  
The HSPLL and ECPLL modes provide the ability to  
selectively run the device at 4 times the external oscil-  
lating source to produce frequencies up to 40 MHz.  
The PLL is enabled by setting the PLLEN bit in the  
OSCTUNE register (Register 3-1).  
Loop  
Filter  
÷4  
VCO  
SYSCLK  
REGISTER 3-1:  
OSCTUNE: PLL CONTROL REGISTER  
U-0  
R/W-0  
PLLEN(1)  
U-0  
U-0  
U-0  
U-0  
U-0  
U-0  
bit 7  
bit 0  
Legend:  
R = Readable bit  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
-n = Value at POR  
bit 7  
bit 6  
Unimplemented: Read as ‘0’  
PLLEN: Frequency Multiplier PLL Enable bit(1)  
1= PLL enabled  
0= PLL disabled  
bit 5-0  
Unimplemented: Read as ‘0’  
Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and reads  
as ‘0’.  
© 2009 Microchip Technology Inc.  
DS39682E-page 29  
 复制成功!