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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
On transitions from RC_RUN mode to PRI_RUN mode,  
the device continues to be clocked from the INTRC  
while the primary clock is started. When the primary  
clock becomes ready, a clock switch to the primary  
clock occurs (see Figure 4-3). When the clock switch is  
complete, the OSTS bit is set and the primary clock is  
providing the device clock. The IDLEN and SCS bits  
are not affected by the switch. The INTRC source will  
continue to run if either the WDT or the Fail-Safe Clock  
Monitor is enabled.  
4.2.3  
RC_RUN MODE  
In RC_RUN mode, the CPU and peripherals are  
clocked from the internal oscillator; the primary clock is  
shut down. This mode provides the best power conser-  
vation of all the Run modes, while still executing code.  
It works well for user applications which are not highly  
timing-sensitive or do not require high-speed clocks at  
all times.  
This mode is entered by setting SCS<1:0> to ‘11’.  
When the clock source is switched to the INTRC (see  
Figure 4-2), the primary oscillator is shut down and the  
OSTS bit is cleared.  
FIGURE 4-2:  
TRANSITION TIMING TO RC_RUN MODE  
Q1 Q2 Q3 Q4 Q1  
Q2  
Q3  
Q4  
Q1  
Q2  
Q3  
1
2
3
n-1  
n
INTRC  
OSC1  
Clock Transition  
CPU  
Clock  
Peripheral  
Clock  
Program  
Counter  
PC  
PC + 2  
PC + 4  
FIGURE 4-3:  
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE  
Q3  
Q4  
Q1  
Q2 Q3 Q4 Q1 Q2 Q3  
Q1  
Q2  
INTRC  
OSC1  
(1)  
TOST  
CPU Clock  
Peripheral  
Clock  
Program  
Counter  
PC + 2  
PC + 4  
PC  
SCS<1:0> bits Changed  
OSTS bit Set  
Note 1: TOST = 1024 TOSC. These intervals are not shown to scale.  
© 2009 Microchip Technology Inc.  
DS39682E-page 37  
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