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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
The primary oscillators include the External Crystal  
and Resonator modes and the External Clock modes.  
The particular mode is defined by the FOSC<2:0>  
Configuration bits. The details of these modes are  
covered earlier in this chapter.  
3.5  
Internal Oscillator Block  
The PIC18F45J10 family of devices includes an inter-  
nal oscillator source (INTRC) which provides a nominal  
31 kHz output. The INTRC is enabled on device  
power-up and clocks the device during its configuration  
cycle until it enters operating mode. INTRC is also  
enabled if it is selected as the device clock source or if  
any of the following are enabled:  
The secondary oscillators are those external sources  
not connected to the OSC1 or OSC2 pins. These  
sources may continue to operate even after the  
controller is placed in a power-managed mode.  
• Fail-Safe Clock Monitor  
• Watchdog Timer  
PIC18F45J10 family devices offer the Timer1 oscillator  
as a secondary oscillator. This oscillator, in all  
power-managed modes, is often the time base for  
functions such as a Real-Time Clock (RTC).  
• Two-Speed Start-up  
These features are discussed in greater detail in  
Section 21.0 “Special Features of the CPU”.  
Most often, a 32.768 kHz watch crystal is connected  
between the RC0/T1OSO/T13CKI and RC1/T1OSI  
pins. Loading capacitors are also connected from each  
pin to ground.  
The INTRC can also be optionally configured as the  
default clock source on device start-up by setting the  
FOSC2 Configuration bit. This is discussed in  
Section 3.6.1 “Oscillator Control Register”.  
The Timer1 oscillator is discussed in greater detail in  
Section 12.3 “Timer1 Oscillator”.  
3.6  
Clock Sources and  
Oscillator Switching  
In addition to being a primary clock source, the internal  
oscillator is available as a power-managed mode  
clock source. The INTRC source is also used as the  
clock source for several special features, such as the  
WDT and Fail-Safe Clock Monitor.  
The PIC18F45J10 family includes a feature that allows  
the device clock source to be switched from the main  
oscillator to an alternate clock source. PIC18F45J10  
family devices offer two alternate clock sources. When  
an alternate clock source is enabled, the various  
power-managed operating modes are available.  
The clock sources for the PIC18F45J10 family devices  
are shown in Figure 3-5. See Section 21.0 “Special  
Features of the CPU” for Configuration register  
details.  
Essentially, there are three clock sources for these  
devices:  
• Primary oscillators  
• Secondary oscillators  
• Internal oscillator  
FIGURE 3-5:  
PIC18F45J10 FAMILY CLOCK DIAGRAM  
PIC18F45J10 Family  
Primary Oscillator  
HS, EC  
OSC2  
Sleep  
HSPLL, ECPLL  
4 x PLL  
OSC1  
Peripherals  
Secondary Oscillator  
T1OSC  
T1OSO  
T1OSCEN  
Enable  
Oscillator  
T1OSI  
Internal Oscillator  
INTRC  
Source  
CPU  
IDLEN  
Clock  
Control  
FOSC<2:0> OSCCON<1:0>  
Clock Source Option  
for Other Modules  
WDT, PWRT, FSCM  
and Two-Speed Start-up  
DS39682E-page 30  
© 2009 Microchip Technology Inc.  
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