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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
4.1.1  
CLOCK SOURCES  
4.0  
POWER-MANAGED MODES  
The SCS<1:0> bits allow the selection of one of three  
clock sources for power-managed modes. They are:  
The PIC18F45J10 family devices provide the ability to  
manage power consumption by simply managing clock-  
ing to the CPU and the peripherals. In general, a lower  
clock frequency and a reduction in the number of circuits  
being clocked constitutes lower consumed power. For  
the sake of managing power in an application, there are  
three primary modes of operation:  
• the primary clock, as defined by the FOSC<1:0>  
Configuration bits  
• the secondary clock (Timer1 oscillator)  
• the internal oscillator  
4.1.2  
ENTERING POWER-MANAGED  
MODES  
• Run mode  
• Idle mode  
• Sleep mode  
Switching from one power-managed mode to another  
begins by loading the OSCCON register. The  
SCS<1:0> bits select the clock source and determine  
which Run or Idle mode is to be used. Changing these  
bits causes an immediate switch to the new clock  
source, assuming that it is running. The switch may  
also be subject to clock transition delays. These are  
discussed in Section 4.1.3 “Clock Transitions and  
Status Indicators” and subsequent sections.  
These modes define which portions of the device are  
clocked and at what speed. The Run and Idle modes  
may use any of the three available clock sources  
(primary, secondary or internal oscillator block); the  
Sleep mode does not use a clock source.  
The power-managed modes include several  
power-saving features offered on previous PIC®  
microcontrollers. One is the clock switching feature,  
offered in other PIC18 devices, allowing the controller  
to use the Timer1 oscillator in place of the primary  
oscillator. Also included is the Sleep mode, offered by  
all PIC microcontrollers, where all device clocks are  
stopped.  
Entry to the power-managed Idle or Sleep modes is  
triggered by the execution of a SLEEPinstruction. The  
actual mode that results depends on the status of the  
IDLEN bit.  
Depending on the current mode and the mode being  
switched to, a change to a power-managed mode does  
not always require setting all of these bits. Many  
transitions may be done by changing the oscillator  
select bits, or changing the IDLEN bit, prior to issuing a  
SLEEP instruction. If the IDLEN bit is already  
configured correctly, it may only be necessary to  
perform a SLEEP instruction to switch to the desired  
mode.  
4.1  
Selecting Power-Managed Modes  
Selecting  
a power-managed mode requires two  
decisions: if the CPU is to be clocked or not and which  
clock source is to be used. The IDLEN bit  
(OSCCON<7>) controls CPU clocking, while the  
SCS<1:0> bits (OSCCON<1:0>) select the clock  
source. The individual modes, bit settings, clock  
sources and affected modules are summarized in  
Table 4-1.  
TABLE 4-1:  
Mode  
POWER-MANAGED MODES  
OSCCON bits Module Clocking  
CPU Peripherals  
Off Off  
Clocked Clocked Primary – HS, EC;  
this is the normal full-power execution mode  
Available Clock and Oscillator Source  
IDLEN<7>(1)  
SCS<1:0>  
Sleep  
0
N/A  
None – All clocks are disabled  
PRI_RUN  
N/A  
10  
SEC_RUN  
RC_RUN  
PRI_IDLE  
SEC_IDLE  
RC_IDLE  
N/A  
N/A  
1
01  
11  
10  
01  
11  
Clocked Clocked Secondary – Timer1 Oscillator  
Clocked Clocked Internal Oscillator  
Off  
Off  
Off  
Clocked Primary – HS, EC  
1
Clocked Secondary – Timer1 Oscillator  
Clocked Internal Oscillator  
1
Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.  
© 2009 Microchip Technology Inc.  
DS39682E-page 35  
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