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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
4.1.3  
CLOCK TRANSITIONS AND STATUS  
INDICATORS  
4.2.2  
SEC_RUN MODE  
The SEC_RUN mode is the compatible mode to the  
“clock switching” feature offered in other PIC18  
devices. In this mode, the CPU and peripherals are  
clocked from the Timer1 oscillator. This gives users the  
option of lower power consumption while still using a  
high-accuracy clock source.  
The length of the transition between clock sources is  
the sum of two cycles of the old clock source and three  
to four cycles of the new clock source. This formula  
assumes that the new clock source is stable.  
Two bits indicate the current clock source and its  
SEC_RUN mode is entered by setting the SCS<1:0>  
bits to ‘01’. The device clock source is switched to the  
Timer1 oscillator (see Figure 4-1), the primary  
oscillator is shut down, the T1RUN bit (T1CON<6>) is  
set and the OSTS bit is cleared.  
status:  
OSTS  
(OSCCON<3>)  
and  
T1RUN  
(T1CON<6>). In general, only one of these bits will be  
set while in a given power-managed mode. When the  
OSTS bit is set, the primary clock is providing the  
device clock. When the T1RUN bit is set, the Timer1  
oscillator is providing the clock. If neither of these bits  
is set, INTRC is clocking the device.  
Note:  
The Timer1 oscillator should already be  
running prior to entering SEC_RUN mode.  
If the T1OSCEN bit is not set when the  
SCS<1:0> bits are set to ‘01’, entry to  
SEC_RUN mode will not occur. If the  
Timer1 oscillator is enabled, but not yet  
running, device clocks will be delayed until  
the oscillator has started. In such situa-  
tions, initial oscillator operation is far from  
stable and unpredictable operation may  
result.  
Note:  
Executing a SLEEP instruction does not  
necessarily place the device into Sleep  
mode. It acts as the trigger to place the  
controller into either Sleep mode or one of  
the Idle modes, depending on the setting  
of the IDLEN bit.  
4.1.4  
MULTIPLE SLEEP COMMANDS  
The power-managed mode that is invoked with the  
SLEEP instruction is determined by the setting of the  
IDLEN bit at the time the instruction is executed. If  
another SLEEP instruction is executed, the device will  
enter the power-managed mode specified by IDLEN at  
that time. If IDLEN has changed, the device will enter the  
new power-managed mode specified by the new setting.  
On transitions from SEC_RUN mode to PRI_RUN  
mode, the peripherals and CPU continue to be clocked  
from the Timer1 oscillator while the primary clock is  
started. When the primary clock becomes ready, a  
clock switch back to the primary clock occurs (see  
Figure 4-2). When the clock switch is complete, the  
T1RUN bit is cleared, the OSTS bit is set and the  
primary clock is providing the clock. The IDLEN and  
SCS bits are not affected by the wake-up; the Timer1  
oscillator continues to run.  
4.2  
Run Modes  
In the Run modes, clocks to both the core and  
peripherals are active. The difference between these  
modes is the clock source.  
4.2.1  
PRI_RUN MODE  
The PRI_RUN mode is the normal, full-power execu-  
tion mode of the microcontroller. This is also the default  
mode upon a device Reset unless Two-Speed Start-up  
is enabled (see Section 21.4 “Two-Speed Start-up”  
for details). In this mode, the OSTS bit is set. (see  
Section 3.6.1 “Oscillator Control Register”).  
FIGURE 4-1:  
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE  
Q1 Q2 Q3 Q4 Q1  
Q2  
Q3  
Q4  
Q1  
Q2  
Q3  
1
2
3
n-1  
n
T1OSI  
OSC1  
Clock Transition  
CPU  
Clock  
Peripheral  
Clock  
Program  
Counter  
PC  
PC + 2  
PC + 4  
DS39682E-page 36  
© 2009 Microchip Technology Inc.  
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