PIC18F45J10 FAMILY
REGISTER 3-2:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
IDLEN
bit 7
U-0
—
U-0
—
U-0
—
R-q(1)
OSTS
U-0
—
R/W-0
SCS1
R/W-0
SCS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1= Device enters an Idle mode on SLEEPinstruction
0= Device enters Sleep mode on SLEEPinstruction
bit 6-4
bit 3
Unimplemented: Read as ‘0’
OSTS: Oscillator Start-up Time-out Status bit(1)
1= Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running
0= Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS<1:0>: System Clock Select bits(4)
11= Internal oscillator
10= Primary oscillator
01= Timer1 oscillator
When FOSC2 = 1:
00= Primary oscillator
When FOSC2 = 0:
00= Internal oscillator
Note 1: The Reset value is ‘0’ when HS mode and Two-Speed Start-up are both enabled; otherwise, it is ‘1’.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
3.7
Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
real-time clock. Other features may be operating that
do not require a device clock source (i.e., MSSP slave,
PSP, INTx pins and others). Peripherals that may add
significant current consumption are listed in
Section 24.2 “DC Characteristics: Power-Down and
Supply Current”.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In RC_RUN and RC_IDLE modes, the internal oscilla-
tor provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 21.2 “Watchdog Timer (WDT)” through
Section 21.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
DS39682E-page 32
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
