PIC18FXX20
BRA
Unconditional Branch
[ label ] BRA
BSF
Bit Set f
Syntax:
n
Syntax:
[ label ] BSF f,b[,a]
Operands:
Operation:
Status Affected:
Encoding:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
1 → f<b>
None
Operation:
Status Affected:
Encoding:
1101
0nnn
nnnn
nnnn
Description:
Add the 2’s complement number
‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a
two-cycle instruction.
1
2
1000
bbba
ffff
ffff
Description:
Bit 'b' in register 'f' is set. If ‘a’ is 0
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
1
1
Words:
Cycles:
Words:
Cycles:
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Write to PC
Q2
Q3
Q4
Write
Decode
Read literal
Process
'n'
Data
Decode
Read
Process
register 'f'
Data
register 'f'
No
operation
No
operation
No
operation
No
operation
BSF
FLAG_REG, 7, 1
Example:
Before Instruction
HERE
BRA Jump
Example:
FLAG_REG
=
=
0x0A
0x8A
Before Instruction
After Instruction
PC
=
=
address (HERE)
address (Jump)
FLAG_REG
After Instruction
PC
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 271
MICROCHIP [ MICROCHIP ]
