PIC18FXX20
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
[ label ] ANDWF
f [,d [,a]
Syntax:
[ label ] BC
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .AND. (f) → dest
N,Z
Operands:
Operation:
-128 ≤ n ≤ 127
if carry bit is ’1’
(PC) + 2 + 2n → PC
Operation:
Status Affected:
Encoding:
Status Affected:
Encoding:
Description:
None
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
If the Carry bit is ‘1’, then the
program will branch.
Description:
The contents of W are AND’ed with
register 'f'. If 'd' is 0, the result is
stored in W. If 'd' is 1, the result is
stored back in register 'f' (default). If
‘a’ is 0, the Access Bank will be
selected. If ‘a’ is 1, the BSR will not
be overridden (default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Process
Data
Q4
Q1
Decode
Q2
Q3
Q4
Write to PC
Decode
Read
Write to
register 'f'
destination
Read literal
Process
'n'
Data
No
No
No
No
ANDWF
REG, 0, 0
Example:
operation
operation
operation
operation
Before Instruction
If No Jump:
Q1
W
=
0x17
0xC2
Q2
Read literal
'n'
Q3
Process
Data
Q4
No
operation
REG
=
Decode
After Instruction
W
=
0x02
0xC2
REG
=
HERE
BC
5
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Carry
PC
=
=
=
=
1;
address (HERE+12)
0;
If Carry
PC
address (HERE+2)
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 267
MICROCHIP [ MICROCHIP ]
