PIC18FXX20
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
[label] CLRF f [,a]
Syntax:
[ label ] CLRWDT
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
000h → f
1 → Z
Operands:
Operation:
None
000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD
TO, PD
Operation:
Status Affected:
Encoding:
Description:
Z
Status Affected:
Encoding:
Description:
0110
101a
ffff
ffff
0000
0000
0000
0100
Clears the contents of the specified
register. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will
be selected as per the BSR value
(default).
1
1
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
1
1
Words:
Cycles:
Words:
Cycles:
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Write
Decode
No
Process
No
operation
Data
operation
Decode
Read
Process
register 'f'
Data
register 'f'
CLRWDT
Example:
CLRF
FLAG_REG,1
Example:
Before Instruction
WDT Counter
=
?
Before Instruction
FLAG_REG
=
=
0x5A
0x00
After Instruction
WDT Counter
WDT Postscaler
TO
=
=
=
=
0x00
After Instruction
0
1
1
FLAG_REG
PD
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 275
MICROCHIP [ MICROCHIP ]
