PIC18CXX2
FIGURE 21-19: MASTER SSP I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-18: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
Symbol Characteristic
Min
Max Units Conditions
No.
THIGH
TLOW
TR
Clock high time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
100
1 MHz mode (1)
100 kHz mode
400 kHz mode
1 MHz mode (1)
100 kHz mode
400 kHz mode
1 MHz mode (1)
100 kHz mode
400 kHz mode
Clock low time
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
101
102
103
90
SDA and SCL
rise time
—
20 + 0.1Cb
—
1000
300
300
ns
ns
ns
Cb is specified to be from
10 to 400 pF
TF
SDA and SCL
fall time
—
20 + 0.1Cb
—
300
300
100
ns
ns
ns
Cb is specified to be from
10 to 400 pF
1 MHz mode (1)
TSU:STA
START condition 100 kHz mode
setup time
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
Only relevant for repeated
400 kHz mode
1 MHz mode (1)
ms START condition
ms
THD:STA START condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms After this period the first
ms clock pulse is generated
ms
91
hold time
400 kHz mode
1 MHz mode (1)
100 kHz mode
400 kHz mode
THD:DAT Data input
0
0
TBD
—
0.9
—
ns
ms
ns
106
107
92
hold time
1 MHz mode (1)
100 kHz mode
400 kHz mode
TSU:DAT Data input
250
100
TBD
—
—
—
ns
ns
ns
Note 2
setup time
1 MHz mode (1)
TSU:STO STOP condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
setup time
400 kHz mode
1 MHz mode (1)
TAA
Output valid from 100 kHz mode
—
—
—
3500
1000
—
ns
ns
ns
109
110
clock
400 kHz mode
1 MHz mode (1)
100 kHz mode
400 kHz mode
TBUF
Bus free time
4.7
1.3
TBD
—
—
—
ms Time the bus must be free
ms before a new transmis-
ms
1 MHz mode (1)
sion can start
D102 Cb
Bus capacitive loading
—
400
pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but parameter #107 ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
parameter #102.+ parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz-mode) before the SCL line is released.
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 267
MICROCHIP [ MICROCHIP ]
