PIC18CXX2
FIGURE 21-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Parm.
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TCY
—
ns
TssL2scL
71
TscH
TscL
TB2B
SCK input high time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25TCY + 30
40
ns Note 1
ns
SCK input low time
(slave mode)
72A
73A
74
ns Note 1
ns Note 2
ns
Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
75
TdoR
SDO data output rise time
PIC18CXXX
—
25
45
25
50
25
45
25
50
100
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LCXXX
76
77
78
TdoF
SDO data output fall time
—
TssH2doZ SS↑ to SDO output hi-impedance
10
TscR
SCK output rise time
(master mode)
PIC18CXXX
—
PIC18LCXXX
—
79
80
TscF
SCK output fall time (master mode)
—
TscH2doV, SDO data output valid after SCK
TscL2doV edge
PIC18CXXX
PIC18LCXXX
PIC18CXXX
PIC18LCXXX
—
—
82
83
TssL2doV SDO data output valid after SS↓
—
—
edge
TscH2ssH, SS ↑ after SCK edge
1.5TCY + 40
TscL2ssH
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter #s 71A and 72A are used.
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 263
MICROCHIP [ MICROCHIP ]
