PIC18CXX2
FIGURE 21-21: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data hold before CK ↓ (DT hold time)
10
—
—
ns
ns
126
TckL2dtl
Data hold after CK ↓ (DT hold time)
15
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 269