PIC18CXX2
FIGURE 21-18: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
TSU:STA START condition
100 kHz mode 2(TOSC)(BRG + 1)
—
—
—
Only relevant for
repeated START
condition
90
Setup time
400 kHz mode 2(TOSC)(BRG + 1)
ns
ns
ns
ns
1 MHz mode (1)
2(TOSC)(BRG + 1)
91
92
93
THD:STA START condition
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
—
—
—
After this period the
first clock pulse is
generated
Hold time
1 MHz mode (1)
2(TOSC)(BRG + 1)
TSU:STO STOP condition
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
—
—
—
Setup time
1 MHz mode (1)
2(TOSC)(BRG + 1)
THD:STO STOP condition
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
—
—
—
Hold time
1 MHz mode (1)
2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
DS39026B-page 266
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
