PIC18CXX2
FIGURE 21-16: I2C BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Parm.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Only relevant for repeated
START condition
91
92
93
THD:STA START condition
Hold time
4000
600
After this period the first
clock pulse is generated
TSU:STO STOP condition
Setup time
4700
600
THD:STO STOP condition
Hold time
4000
600
DS39026B-page 264
Preliminary
7/99 Microchip Technology Inc.