PIC18F2331/2431/4331/4431
Four of the PORTB pins (RB<7:4>) have an interrupt-
11.2 PORTB, TRISB and LATB
Registers
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB<7:4>)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB<7:4>
are ORed together to generate the RB port change
interrupt with flag bit, RBIF (INTCON<0>).
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTBinstruction).
b) NOP(or any 1 TCY delay).
EXAMPLE 11-2:
INITIALIZING PORTB
c) Clear flag bit, RBIF.
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB and waiting 1 TCY will end the
mismatch condition and allow flag bit, RBIF, to be
cleared. Also, if the port pin returns to its original state,
the mismatch condition will be cleared.
CLRF
LATB
MOVLW
MOVWF
0xCF
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
TRISB
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
RB<3:0> and RB4 pins are multiplexed with the 14-bit
PWM module for PWM<3:0> and PWM5 output. The
RB5 pin can be configured by the Configuration bit,
PWM4MX, as the alternate pin for PWM4 output.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
DS39616D-page 116
2010 Microchip Technology Inc.
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