PIC18F2331/2431/4331/4431
11.1 PORTA, TRISA and LATA
Registers
11.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Each port has three registers for its operation. These
registers are:
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
The Data Latch register (LATA) is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
• LAT register (Data Latch)
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
The RA<4:2> pins are multiplexed with three input
capture pins and Quadrature Encoder Interface pins.
Pins, RA6 and RA7, are multiplexed with the main
oscillator pins. They are enabled as oscillator or I/O
pins by the selection of the main oscillator in
Configuration Register 1H (see Section 23.1
“Configuration Bits” for details). When they are not
used as port pins, RA6 and RA7 and their associated
TRIS and LAT bits are read as ‘0’.
A simplified model of a generic I/O port without the
interfaces to other peripherals is shown in Figure 11-1.
FIGURE 11-1:
GENERIC I/O PORT
OPERATION
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the com-
parator voltage reference output. The operation of pins
RA<3:0> and RA5 as A/D Converter inputs is selected
by clearing/setting the control bits in the ANSEL0 and
ANSEL1 registers.
RD LAT
Data
Bus
D
Q
I/O Pin(1)
WR LAT
or
PORT
CK
Data Latch
Note 1: On a Power-on Reset, RA<5:0> are
configured as analog inputs and read as ‘0’.
D
Q
2: RA5 I/F is available only on 40-pin
WR TRIS
RD TRIS
devices (PIC18F4331/4431).
CK
TRIS Latch
Input
Buffer
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Q
D
EXAMPLE 11-1:
INITIALIZING PORTA
CLRF
PORTA
LATA
0x3F
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
EN
EN
RD PORT
CLRF
Note 1: I/O pins have diode protection to VDD and VSS.
MOVLW
MOVWF
MOVLW
; Configure A/D
ANSEL0 ; for digital inputs
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
2010 Microchip Technology Inc.
DS39616D-page 113
MICROCHIP [ MICROCHIP ]
