PIC18F2331/2431/4331/4431
10.6 INTx Pin Interrupts
10.7 TMR0 Interrupt
External interrupts on the INT0, INT1 and INT2 pins are
edge-triggered. If the corresponding INTEDGx bit in the
INTCON2 register is set (= 1), the interrupt is triggered
by a rising edge. If the bit is clear, the trigger is on the
falling edge.
In 8-bit mode (which is the default), an overflow
(FFh 00h) in the TMR0 register will set flag bit,
TMR0IF. In 16-bit mode, an overflow (FFFFh 0000h)
in the TMR0H:TMR0L registers will set flag bit,
TMR0IF. The interrupt can be enabled/disabled by
setting/clearing enable bit, TMR0IE (INTCON<5>).
Interrupt priority for Timer0 is determined by the value
contained in the interrupt priority bit, TMR0IP
(INTCON2<2>). See Section 12.0 “Timer0 Module”
for further details.
When a valid edge appears on the INTx pin, the corre-
sponding flag bit, INTxIF, is set. This interrupt can be
disabled by clearing the corresponding enable bit,
INTxIE. Before re-enabling the interrupt, the flag bit,
INTxIF, must be cleared in software in the Interrupt
Service Routine.
10.8 PORTB Interrupt-on-Change
All external interrupts (INT0, INT1 and INT2) can wake-
up the processor from the Idle or Sleep modes if bit,
INTxIE, was set prior to going into those modes. If the
Global Interrupt Enable bit, GIE, is set, the processor
will branch to the interrupt vector following wake-up.
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
Interrupt priority for INT1 and INT2 is determined by
the value contained in the Interrupt Priority bits,
INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>).
There is no priority bit associated with INT0. It is
always a high-priority interrupt source.
10.9 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 6.1.3
“Fast Register Stack”), the user may need to save the
WREG, STATUS and BSR registers on entry to the
Interrupt Service Routine. Depending on the user’s
application, other registers may also need to be saved.
Example 10-1 saves and restores the WREG, STATUS
and BSR registers during an Interrupt Service Routine.
EXAMPLE 10-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
DS39616D-page 112
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
