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PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
TABLE 11-3: PORTB I/O SUMMARY  
TRIS  
Setting  
I/O  
Pin  
Function  
I/O  
Description  
Type  
RB0/PWM0  
RB0  
0
1
O
I
DIG  
TTL  
LATB<0> data output; not affected by analog input.  
PORTB<0> data input; weak pull-up when RBPU bit is cleared.  
Disabled when analog input is enabled.  
PWM0  
RB1  
0
0
1
O
O
I
DIG  
DIG  
TTL  
PWM Output 0.  
RB1/PWM1  
LATB<1> data output; not affected by analog input.  
PORTB<1> data input; weak pull-up when RBPU bit is cleared.  
Disabled when analog input is enabled.  
PWM1  
RB2  
0
0
1
O
O
I
DIG  
DIG  
TTL  
PWM Output 1.  
RB2/PWM2  
LATB<2> data output; not affected by analog input.  
PORTB<2> data input; weak pull-up when RBPU bit is cleared.  
Disabled when analog input is enabled.  
PWM2  
RB3  
0
0
1
O
O
I
DIG  
DIG  
TTL  
PWM Output 2.  
RB3/PWM3  
LATB<3> data output; not affected by analog input.  
PORTB<3> data input; weak pull-up when RBPU bit is cleared.  
Disabled when analog input is enabled.  
PWM3  
RB4  
0
0
1
O
O
I
DIG  
DIG  
TTL  
PWM Output 3.  
RB4/KBI0/PWM5  
LATB<4> data output; not affected by analog input.  
PORTB<4> data input; weak pull-up when RBPU bit is cleared.  
Disabled when analog input is enabled.  
KBI0  
PWM5  
RB5  
1
0
0
1
1
0
x
I
O
O
I
TTL  
DIG  
DIG  
TTL  
TTL  
DIG  
ST  
Interrupt-on-change pin.  
PWM Output 5.  
RB5/KBI1/  
PWM4/PGM  
LATB<5> data output.  
PORTB<5> data input; weak pull-up when RBPU bit is cleared.  
Interrupt-on-change pin.  
KBI1  
I
(3)  
PWM4  
O
I
PWM Output 4; takes priority over port data.  
(2)  
PGM  
Single-Supply Programming mode entry (ICSP™). Enabled by LVP  
Configuration bit; all other pin functions are disabled.  
RB6/KBI2/PGC  
RB7/KBI3/PGD  
RB6  
0
1
1
x
0
1
1
x
x
O
I
DIG  
TTL  
TTL  
ST  
LATB<6> data output.  
PORTB<6> data input; weak pull-up when RBPU bit is cleared.  
Interrupt-on-change pin.  
KBI2  
PGC  
RB7  
I
(1)  
I
Serial execution (ICSP™) clock input for ICSP and ICD operation.  
LATB<7> data output.  
O
I
DIG  
TTL  
TTL  
DIG  
ST  
PORTB<7> data input; weak pull-up when RBPU bit is cleared.  
Interrupt-on-change pin.  
KBI3  
PGD  
I
(1)  
O
I
Serial execution data output for ICSP and ICD operation.  
(1)  
Serial execution data input for ICSP and ICD operation.  
Legend:  
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;  
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).  
Note 1: All other pin functions are disabled when ICSP or ICD is enabled.  
2: Single-Supply Programming must be enabled.  
3: RD5 is the alternate pin for PWM4.  
2010 Microchip Technology Inc.  
DS39616D-page 117  
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