PIC18F2331/2431/4331/4431
TABLE 11-5: PORTC I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RC0/T1OSO/
T1CKI
RC0
0
1
x
O
I
DIG
ST
LATC<0> data output.
PORTC<0> data input.
T1OSO
O
ANA
Timer1 oscillator output; enabled when Timer1 oscillator is enabled.
Disables digital I/O.
T1CKI
RC1
1
0
1
x
I
O
I
ST
DIG
ST
Timer1/Timer3 counter input.
LATC<1> data output.
RC1/T1OSI/
CCP2/FLTA
PORTC<1> data input.
T1OSI
CCP2
I
ANA
Timer1 oscillator input; enabled when Timer1 oscillator is enabled.
Disables digital I/O.
0
1
1
0
1
0
1
1
0
1
1
1
1
0
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
O
I
DIG
ST
CCP2 compare and PWM output; takes priority over port data.
CCP2 capture input.
FLTA
RC2
I
ST
Fault Interrupt Input Pin A.
LATC<2> data output.
RC2/CCP1/FLTB
O
I
DIG
ST
PORTC<2> data input.
CCP1
O
I
DIG
ST
CCP1 compare or PWM output; takes priority over port data.
CCP1 capture input.
FLTB
RC3
I
ST
Fault Interrupt Input Pin B.
LATC<3> data output.
RC3/T0CKI/
T5CKI/INT0
O
I
DIG
ST
PORTC<3> data input.
(1)
T0CKI
I
ST
Timer0 alternate clock input.
Timer5 alternate clock input.
External Interrupt 0.
(1)
T5CKI
I
ST
INT0
RC4
I
ST
RC4/INT1/SDI/
SDA
O
I
DIG
ST
LATC<4> data output.
PORTC<4> data input.
INT1
I
ST
External Interrupt 1.
(1)
SDI
I
ST
SPI data input (SSP module).
(1)
2
SDA
O
I
DIG
I C™ data output (SSP module); takes priority over port data.
2
2
I C
I C data input (SSP module).
RC5/INT2/SCK/
SCL
RC5
O
I
DIG
ST
LATC<5> data output.
PORTC<5> data input.
INT2
I
ST
External Interrupt 2.
(1)
SCK
O
I
DIG
ST
SPI clock output (SSP module); takes priority over port data.
SPI clock input (SSP module).
(1)
2
SCL
O
I
DIG
I C clock output (SSP module); takes priority over port data.
2
2
I C
I C clock input (SSP module); input type depends on module setting.
RC6/TX/CK/SS
RC6
O
I
DIG
ST
LATC<6> data output.
PORTC<6> data input.
TX
CK
O
DIG
Asynchronous serial transmit data output (EUSART module);
takes priority over port data. User must configure as an output.
0
O
DIG
Synchronous serial clock output (EUSART module); takes priority
over port data.
1
1
I
I
ST
ST
Synchronous serial clock input (EUSART module).
SPI slave select input.
SS
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RD0 is the alternate pin for T0CKI/T5CKI; RD2 is the alternate pin for SDI/SDA; RD3 is the alternate pin for SCK/SCL;
RD1 is the alternate pin for SDO.
DS39616D-page 120
2010 Microchip Technology Inc.
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