PIC18F2331/2431/4331/4431
TABLE 11-1: PORTA I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
RA0/AN0
Function
I/O
Description
RA0
0
1
1
O
I
DIG LATA<0> data output; not affected by analog input.
TTL PORTA<0> data input; disabled when analog input is enabled.
AN0
RA1
I
ANA A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
RA1/AN1
0
1
1
O
I
DIG LATA<1> data output; not affected by analog input.
TTL PORTA<1> data input; disabled when analog input is enabled.
AN1
RA2
I
ANA A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
RA2/AN2/VREF-/
CAP1/INDX
0
1
1
1
1
1
O
I
DIG LATA<2> data output; not affected by analog input.
TTL PORTA<2> data input. Disabled when analog input is enabled.
ANA A/D Input Channel 2. Default input configuration on POR.
ANA A/D voltage reference low input.
AN2
VREF-
CAP1
INDX
I
I
I
ST
ST
Input Capture Pin 1. Disabled when analog input is enabled.
I
Quadrature Encoder Interface index input pin. Disabled when analog
input is enabled.
RA3/AN3/VREF+/
CAP2/QEA
RA3
0
1
1
1
1
1
O
I
DIG LATA<3> data output; not affected by analog input.
TTL PORTA<3> data input; disabled when analog input is enabled.
ANA A/D Input Channel 3. Default input configuration on POR.
ANA A/D voltage reference high input.
AN3
VREF+
CAP2
QEA
I
I
I
ST
ST
Input Capture Pin 2. Disabled when analog input is enabled.
I
Quadrature Encoder Interface Channel A input pin. Disabled when
analog input is enabled.
RA4/AN4/CAP3/
QEB
RA4
0
1
1
1
1
O
I
DIG LATA<4> data output; not affected by analog input.
ST PORTA<4> data input; disabled when analog input is enabled.
ANA A/D Input Channel 4. Default input configuration on POR.
AN4
CAP3
QEB
I
I
ST
ST
Input Capture Pin 3. Disabled when analog input is enabled.
I
Quadrature Encoder Interface Channel B input pin. Disabled when
analog input is enabled.
RA5/AN5/LVDIN
OSC2/CLKO/RA6
RA5
0
1
1
1
x
x
O
I
DIG LATA<5> data output; not affected by analog input.
TTL PORTA<5> data input; disabled when analog input is enabled.
ANA A/D Input Channel 5. Default configuration on POR.
ANA Low-Voltage Detect external trip point input.
AN5
I
LVDIN
OSC2
CLKO
I
O
O
ANA Main oscillator feedback output connection (XT, HS and LP modes).
DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator
modes.
RA6
0
1
x
x
0
1
O
I
DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.
ANA Main oscillator input connection.
OSC1
CLKI
RA7
I
OSC1/CLKI/RA7
I
ANA Main clock input connection.
O
I
DIG LATA<7> data output. Disabled in external oscillator modes.
TTL PORTA<7> data input. Disabled in external oscillator modes.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
DS39616D-page 114
2010 Microchip Technology Inc.
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