PIC17C75X
TABLE 5-4:
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (Cont.’d)
Power-on Reset
Brown-out Reset
MCLR Reset
WDT Reset
Wake-up from SLEEP
through interrupt
Register
Address
Bank 2
TMR1
10h
11h
12h
13h
14h
15h
16h
17h
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR2
TMR3L
TMR3H
PR1
PR2
PR3/CA1L
PR3/CA1H
Bank 3
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
10h
11h
12h
13h
14h
15h
16h
17h
xx-- ----
xx0- ----
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
uu-- ----
uu0- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uu-- ----
uuu- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
CA2H
TCON1
TCON2
Bank 4
uuu- uuuu(1)
uuu- uuuu
---- ----
uuuu -uuu
uuuu uuuu
uuuu --uu
uuuu uuuu
uuuu uuuu
PIR2
10h
000- 0010
000- 0010
PIE2
11h
12h
13h
14h
15h
16h
17h
000- 0000
---- ----
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
xxxx xxxx
000- 0000
---- ----
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
uuuu uuuu
Unimplemented
RCSTA2
RCREG2
TXSTA2
TXREG2
SPBRG2
Bank 5
DDRF
10h
11h
12h
13h
14h
15h
16h
17h
1111 1111
xxxx xxxx
1111 1111
xxxx xxxx
0000 -0-0
000- 0000
xxxx xxxx
xxxx xxxx
1111 1111
uuuu uuuu
1111 1111
uuuu uuuu
0000 -0-0
000- 0000
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PORTF
DDRG
PORTG
ADCON0
ADCON1
ADRESL
ADRESH
Legend: u= unchanged, x= unknown, -= unimplemented read as '0', q= value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: If Brown-out is enabled, else the BOR bit is unknown.
DS30264A-page 26
Preliminary
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
