PIC17C75X
FIGURE 16-7: FLOWCHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
Yes
Yes
Start of A/D
Conversion Delayed
1 Instruction Cycle
Finish Conversion
SLEEP
Instruction?
A/D Clock
= RC?
GO = 0,
ADIF = 1
No
No
Yes
Yes
Abort Conversion
GO = 0,
Wake-up
From Sleep?
Finish Conversion
Device in
SLEEP?
Wait 2TAD
GO = 0,
ADIF = 1
ADIF = 0
No
No
SLEEP
Power-down A/D
Finish Conversion
Stay in Sleep
Power-down A/D
Wait 2TAD
GO = 0,
ADIF = 1
Wait 2TAD
TABLE 16-3: REGISTERS/BITS ASSOCIATED WITH A/D
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other Resets
(Note 1)
06h, unbanked CPUSTA
07h, unbanked INTSTA
—
—
STAKAV GLINTD
TO
PD
POR
T0IE
BOR
INTE
--11 1100
0000 0000
--11 qq11
0000 0000
000- 0010
PEIF
T0CKIF
BCLIF
BCLIE
T0IF
ADIF
ADIE
INTF
—
PEIE
T0CKIE
CA3IF
CA3IE
10h, Bank 4
11h, Bank 4
10h, Bank 5
11h, Bank 5
PIR2
SSPIF
SSPIE
CA4IF
CA4IE
TX2IF
TX2IE
RC2IF 000- 0010
PIE2
—
RC2IE 000- 0000
000- 0000
1111 1111
1111 1111
DDRF
PORTF
Data Direction register for PORTF
0000 0000
0000 0000
RF7/
AN11
RF6/
AN10
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
1111 1111
1111 1111
uuuu 0000
12h, Bank 5
13h, Bank 5
DDRG
Data Direction register for PORTG
RG3/
AN0/VREF+
xxxx 0000
PORTG
RG7/ RG6/ RG5/
TX2/CK2 RX2/DT2 PWM3
RG4/
CAP3
RG2/
AN1/VREF
-
RG1/
AN2
RG0/
AN3
ADCON0
ADCON1
CHS3
CHS2
CHS1
ADFM
CHS0
—
—
GO/DONE
PCFG2
—
ADON 0000 -0-0
0000 -0-0
000- 0000
uuuu uuuu
uuuu uuuu
14h, Bank 5
15h, Bank 5
16h, Bank 5
ADCS1
ADCS0
PCFG3
PCFG1 PCFG0 000- 0000
xxxx xxxx
ADRESL A/D Result Low Register
ADRESH A/D Result High Register
xxxx xxxx
17h, Bank 5
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 175
MICROCHIP [ MICROCHIP ]
