PIC17C75X
17.3.2 CLEARING THE WDT AND POSTSCALER
The WDT and postscaler are cleared when:
17.3
Watchdog Timer (WDT)
The Watchdog Timer’s function is to recover from
software malfunction. The WDT uses an internal free
running on-chip RC oscillator for its clock source. This
does not require any external components. This RC
oscillator is separate from the RC oscillator of the
OSC1/CLKIN pin. That means that the WDT will run,
even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins have been stopped, for example,
by execution of a SLEEP instruction. During normal
• The device is in the reset state
• A SLEEPinstruction is executed
• A CLRWDTinstruction is executed
• Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
first edge after the device exits the reset state.
17.3.3 WDT PROGRAMMING CONSIDERATIONS
operation and SLEEP mode,
a WDT time-out
generates a device RESET. The WDT can be
permanently disabled by programming the configura-
tion bits WDTPS1:WDTPS0 as '00' (Section 17.1).
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT postscaler) it may take several seconds before a
WDT time-out occurs.
Under normal operation, the WDT must be cleared on
a regular interval. This time is less the minimum WDT
overflow time. Not clearing the WDT in this time frame
will cause the WDT to overflow and reset the device.
The WDT and postscaler is the Power-up Timer during
the Power-on Reset sequence.
17.3.4 WDT AS NORMAL TIMER
17.3.1 WDT PERIOD
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The over-
flow time is 65536 TOSC cycles. On overflow, the TO bit
is cleared (device is not reset).The CLRWDTinstruction
can be used to set the TO bit. This allows the WDT to
be a simple overflow timer. The simple timer does not
increment when in sleep.
The WDT has a nominal time-out period of 12 ms, (with
postscaler = 1).The time-out periods vary with temper-
DD
ature, V and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
postscaler with a division ratio of up to 1:256 can be
assigned to the WDT. Thus, typical time-out periods up
to 3.0 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out thus generating a device RESET
condition.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
FIGURE 17-2: WATCHDOG TIMER BLOCK DIAGRAM
On-chip RC
Oscillator
WDT
Postscaler
(1)
WDTPS1:WDTPS0
4 - to - 1 MUX
WDT Overflow
WDT Enable
Note 1: This oscillator is separate from the external
RC oscillator on the OSC1 pin.
TABLE 17-2: REGISTERS/BITS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
POR,
BOR
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
Config
See Figure 17-1 for location of WDTPSx bits in Configuration Word.
STKAV GLINTD TO PD
(Note 2)
(Note 2)
06h, Unbanked CPUSTA
—
—
POR
BOR
--11 1100 --11 qq11
Legend: -= unimplemented read as '0', q- value depends on condition, shaded cells are not used by the WDT.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
2: This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 179
MICROCHIP [ MICROCHIP ]
