PIC17C75X
FIGURE 16-2: ADCON1 REGISTER (ADDRESS 15h, BANK 5)
R/W-0 R/W-0
ADCS1 ADCS0
bit7
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PCFG3
PCFG2
PCFG1
PCFG0
R =Readable bit
W = Writable bit
U =Unimplemented
bit, read as ‘0’
bit0
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/8
01= FOSC/32
10= FOSC/64
11= FRC (clock derived from an internal RC oscillator)
bit 5:
bit 4:
ADFM: A/D Result format select
1 = Right justified. 6 Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ’0’.
Unimplemented: Read as '0'
bit 3-0: PCFG3:PCFG1: A/D Port Configuration Control bits
PCFG3:PCFG1 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
000
001
010
011
100
101
110
111
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
bit 0:
PCFG0: A/D Voltage Reference Select bit
1 = A/D reference is the VREF+ and VREF- pins
0 = A/D reference is AVDD and AVSS
Note:When this bit is set, ensure that the A/D voltage reference specifications are met.
DS30264A-page 168
Preliminary
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
