PIC16F/LF1946/47
7.5.5
PIE4 REGISTER
The PIE4 register contains the interrupt enable bits, as
shown in Register 7-5.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-5:
PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
U-0
—
U-0
—
R/W-0/0
RC2IE
R/W-0/0
TX2IE
U-0
—
U-0
—
R/W-0/0
BCL2IE
R/W-0/0
SSP2IE
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IE: USART2 Receive Interrupt Enable bit
1= Enables the USART2 receive interrupt
0= Disables the USART2 receive interrupt
bit 4
TX2IE: USART2 Transmit Interrupt Enable bit
1= Enables the USART2 transmit interrupt
0= Disables the USART2 transmit interrupt
bit 3-2
bit 1
Unimplemented: Read as ‘0’
BCL2IE: MSSP2 Bus Collision Interrupt Enable bit
1= Enables the MSSP2 Bus Collision Interrupt
0= Disables the MSSP2 Bus Collision Interrupt
bit 0
SSP2IE: Synchronous Serial Port (MSSP2) Interrupt Enable bit
1= Enables the MSSP2 interrupt
0= Disables the MSSP2 interrupt
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 93
MICROCHIP [ MICROCHIP ]
