PIC16F/LF1946/47
7.5.2
PIE1 REGISTER
The PIE1 register contains the interrupt enable bits, as
shown in Register 7-2.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
TMR1GIE
bit 7
R/W-0/0
ADIE
R/W-0/0
RCIE
R/W-0/0
TXIE
R/W-0/0
SSPIE
R/W-0/0
CCP1IE
R/W-0/0
TMR2IE
R/W-0/0
TMR1IE
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR1GIE: Timer1 Gate Interrupt Enable bit
1= Enables the Timer1 Gate Acquisition interrupt
0= Disables the Timer1 Gate Acquisition interrupt
ADIE: A/D Converter (ADC) Interrupt Enable bit
1= Enables the ADC interrupt
0= Disables the ADC interrupt
RCIE: USART1 Receive Interrupt Enable bit
1= Enables the USART1 receive interrupt
0= Disables the USART1 receive interrupt
TXIE: USART1 Transmit Interrupt Enable bit
1= Enables the USART1 transmit interrupt
0= Disables the USART1 transmit interrupt
SSPIE: Synchronous Serial Port (MSSP1) Interrupt Enable bit
1= Enables the MSSP1 interrupt
0= Disables the MSSP1 interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the Timer2 to PR2 match interrupt
0= Disables the Timer2 to PR2 match interrupt
TMR1IE: Timer1 Overflow Interrupt Enable bit
1= Enables the Timer1 overflow interrupt
0= Disables the Timer1 overflow interrupt
DS41414A-page 90
Preliminary
2010 Microchip Technology Inc.
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