PIC16F/LF1946/47
7.5.9
PIR4 REGISTER
The PIR4 register contains the interrupt flag bits, as
shown in Register 7-9.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-9:
PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
U-0
—
U-0
—
R/W-0/0
RC2IF
R/W-0/0
TX2IF
U-0
—
U-0
—
R/W-0/0
BCL2IF
R/W-0/0
SSP2IF
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IF: USART2 Receive Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 4
TX2IF: USART2 Transmit Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 3-2
bit 1
Unimplemented: Read as ‘0’
BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 0
SSP2IF: Synchronous Serial Port (MSSP2) Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 97
MICROCHIP [ MICROCHIP ]
