PIC16F/LF1946/47
7.5.4
PIE3 REGISTER
The PIE3 register contains the interrupt enable bits, as
shown in Register 7-4.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-4:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
—
R/W-0/0
CCP5IE
R/W-0/0
CCP4IE
R/W-0/0
CCP3IE
R/W-0/0
TMR6IE
U-0
—
R/W-0/0
TMR4IE
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
Unimplemented: Read as ‘0’
CCP5IE: CCP5 Interrupt Enable bit
1= Enables the CCP5 interrupt
0= Disables the CCP5 interrupt
bit 5
bit 4
bit 3
CCP4IE: CCP4 Interrupt Enable bit
1= Enables the CCP4 interrupt
0= Disables the CCP4 interrupt
CCP3IE: CCP3 Interrupt Enable bit
1= Enables the CCP3 interrupt
0= Disables the CCP3 interrupt
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1= Enables the TMR6 to PR6 Match interrupt
0= Disables the TMR6 to PR6 Match interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1= Enables the TMR4 to PR4 Match interrupt
0= Disables the TMR4 to PR4 Match interrupt
bit 0
Unimplemented: Read as ‘0’
DS41414A-page 92
Preliminary
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
