PIC16F/LF1946/47
7.5.7
PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 7-7.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-7:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
OSFIF
R/W-0/0
C2IF
R/W-0/0
C1IF
R/W-0/0
EEIF
R/W-0/0
BCLIF
R/W-0/0
LCDIF
U-0
—
R/W-0/0
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
OSFIF: Oscillator Fail Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
C2IF: Comparator C2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
C1IF: Comparator C1 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
EEIF: EEPROM Write Completion Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
BCLIF: MSSP1 Bus Collision Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
LCDIF: LCD Module Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 1
bit 0
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 95
MICROCHIP [ MICROCHIP ]
