PIC16F/LF1946/47
FIGURE 24-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXxREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TXx/CKx
pin
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
Word 2
1 TCY
Word 1
TXxIF bit
(Interrupt Reg. Flag)
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg
Transmit Shift Reg
Note:
This timing diagram shows two consecutive transmissions.
TABLE 24-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON ABDOVF
BAUD2CON ABDOVF
RCIDL
RCIDL
PEIE
ADIE
—
—
SCKP
SCKP
INTE
BRG16
BRG16
IOCIE
SSP1IE
—
—
—
WUE
WUE
ABDEN
ABDEN
IOCIF
300
300
89
—
INTCON
PIE1
GIE
—
TMR0IE
RC1IE
RC2IE
RC1IF
RC2IF
SREN
SREN
TMR0IF
CCP1IE
—
INTF
TX1IE
TX2IE
TX1IF
TX2IF
CREN
CREN
TMR2IE
BCL2IE
TMR2IF
BCL2IF
OERR
OERR
TMR1IE
SSP2IE
TMR1IF
SSP2IF
RX9D
90
PIE4
—
93
PIR1
—
ADIF
—
SSP1IF
—
CCP1IF
—
94
PIR4
—
93
RC1STA
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TX1REG
TX1STA
TX2REG
TX2STA
SPEN
SPEN
RX9
RX9
ADDEN
ADDEN
FERR
FERR
299
299
301*
301*
301*
301*
291*
298
291*
298
RX9D
EUSART1 Baud Rate Generator, Low Byte
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, High Byte
EUSART1 Transmit Register
CSRC
CSRC
TX9
TX9
TXEN
SYNC
EUSART2 Transmit Register
SYNC SENDB
SENDB
BRGH
TRMT
TRMT
TX9D
TX9D
TXEN
BRGH
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission.
Page provides register information.
*
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 293
MICROCHIP [ MICROCHIP ]
