PIC16F/LF1946/47
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
24.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
Note:
The PIC16F/LF/1946/47 devices have two
EUSARTs. Therefore, all information in
this section refers to both EUSART 1 and
EUSART 2.
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
• Programmable clock and data polarity
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
system.
Full-Duplex
mode
is
useful
for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 24-1 and Figure 24-2.
FIGURE 24-1:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXxIE
Interrupt
TXxIF
TXxREG Register
8
TXx/CKx pin
MSb
(8)
LSb
0
Pin Buffer
and Control
• • •
Transmit Shift Register (TSR)
TXEN
TRMT
Baud Rate Generator
BRG16
FOSC
÷ n
TX9
n
+ 1
Multiplier x4
x16 x64
TX9D
SYNC
BRGH
BRG16
1
X
X
X
1
1
0
1
0
0
0
1
0
0
0
SPxBRGH SPxBRGL
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 289
MICROCHIP [ MICROCHIP ]
