PIC16F/LF1946/47
FIGURE 24-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RXx/DTx pin
bit 7/8
bit 7/8
bit 0 bit 1
Stop
bit
Stop
bit
Stop
bit
bit 0
bit 7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
RCxREG
Word 1
RCxREG
RCIDL
Read Rcv
Buffer Reg
RCxREG
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.
TABLE 24-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON
BAUD2CON
INTCON
PIE1
ABDOVF
RCIDL
RCIDL
PEIE
ADIE
—
—
SCKP
SCKP
INTE
BRG16
BRG16
IOCIE
SSP1IE
—
—
—
WUE
WUE
ABDEN
ABDEN
IOCIF
300
300
89
ABDOVF
—
GIE
—
TMR0IE
RC1IE
RC2IE
RC1IF
RC2IF
TMR0IF
CCP1IE
—
INTF
TX1IE
TX2IE
TX1IF
TX2IF
TMR2IE
BCL2IE
TMR2IF
BCL2IF
TMR1IE
SSP2IE
TMR1IF
SSP2IF
90
PIE4
—
93
PIR1
—
ADIF
—
SSP1IF
—
CCP1IF
—
94
PIR4
—
93
RC1REG
RC1STA
RC2REG
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TRISC
EUSART1 Receive Register
SREN CREN ADDEN
EUSART2 Receive Register
SREN CREN ADDEN
294*
299
294*
299
301*
301*
301*
301*
130
298
298
SPEN
SPEN
RX9
RX9
FERR
FERR
OERR
OERR
RX9D
RX9D
EUSART1 Baud Rate Generator, Low Byte
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, High Byte
TRISC7
CSRC
CSRC
TRISC6
TX9
TRISC5 TRISC4 TRISC3
TRISC2
BRGH
BRGH
TRISC1
TRMT
TRMT
TRISC0
TX9D
TX1STA
TX2STA
TXEN
TXEN
SYNC
SYNC
SENDB
SENDB
TX9
TX9D
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.
Page provides register information.
*
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 297
MICROCHIP [ MICROCHIP ]
