Figure 18-16. Amplifier Synchronization Timing Diagram
ADSC is Set when the Amplifier Output is Changing due to the Amplifier Clock Switch
Signal to be
measured
PSC
Block
PSCn_ASY
AMPLI_clk
(Sync Clock
CK ADC
Amplifier
Block
Amplifier Sample
Enable
Amplifier Hold
Value
Valid sample
ADSC
ADC
ADC
Sampling
Aborted
ADC
Activity
ADC
Conv
ADC
Conv
ADC
Sampling
ADC
Sampling
ADC Result
Ready
ADC Result
Ready
In order to have a better understanding of the functioning of the amplifier synchronization, a timing diagram example is
shown Figure 18-15 on page 215.
It is also possible to auto trigger conversion on the amplified channel. In this case, the conversion is started at the next
amplifier clock event following the last auto trigger event selected thanks to the ADTS bits in the ADCSRB register. In auto
trigger conversion, the free running mode is not possible unless the ADSC bit in ADCSRA is set by soft after each
conversion.
216
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
