• Bit 4– ADIF: ADC Interrupt Flag
Set by hardware as soon as a conversion is complete and the data register are updated with the conversion result.
Cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF can be cleared by writing it to logical one.
• Bit 3– ADIE: ADC Interrupt Enable Bit
Set this bit to activate the ADC end of conversion interrupt.
Clear it to disable the ADC end of conversion interrupt.
• Bit 2, 1, 0– ADPS2, ADPS1, ADPS0: ADC Prescaler Selection Bits
These 3 bits determine the division factor between the system clock frequency and input clock of the ADC.
The different setting are shown in Table 18-6.
.
Table 18-6. ADC Prescaler Selection
ADPS2
ADPS1
ADPS0
Division Factor
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
2
4
8
16
32
64
128
18.9.3 ADC control and status register B– ADCSRB
Bit
7
6
5
4
-
3
ADTS3
R/W
0
2
ADTS2
R/W
0
1
ADTS1
R/W
0
0
ADHSM ISRCEN AREFEN
ADTS0 ADCSRB
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R
0
R/W
0
• Bit 7 – ADHSM: ADC High-speed Mode
Writing this bit to one enables the ADC high-speed mode. Set this bit if you wish to convert with an ADC clock frequency
higher than 200KHz.
Clear this bit to reduce the power consumption of the ADC when the ADC clock frequency is lower than 200KHz.
• Bit 6 – ISRCEN: Current Source Enable
Set this bit to source a 100µA current to the AREF pin.
Clear this bit to use AREF pin as analog reference pin.
• Bit 5 – AREFEN: Analog Reference pin Enable
Set this bit to connect the internal AREF circuit to the AREF pin.
Clear this bit to disconnect the internal AREF circuit from the AREF pin.
• Bit 4 – Res: Reserved Bit
This bit is unused bit in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 3, 2, 1, 0– ADTS3:ADTS0: ADC Auto Trigger Source Selection Bits
These bits are only necessary in case the ADC works in auto trigger mode. It means if ADATE bit in ADCSRA register is set.
In accordance with Table 18-6 on page 212, these 3 bits select the interrupt event which will generate the trigger of the start
of conversion. The start of conversion will be generated by the rising edge of the selected interrupt flag whether the interrupt
is enabled or not. In case of trig on PSCnASY event, there is no flag. So in this case a conversion will start each time the trig
event appears and the previous conversion is completed.
212
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
