The block diagram of the two amplifiers is shown on Figure 18-17.
Figure 18-17. Amplifiers Block Diagram
AMP0+
+
-
Toward ADC MUX
(AMP0)
AMP0-
ADCK/8
00
01
10
Timer 0 Compare Match
Timer 0 Overflow
Timer 1 Compare Match
Timer 1 Overflow
PSS0
Amplifier 0
Clock
01
PSS1
PSS2
AMP0EN AMP0IS AMP0G1 AMP0G0 AMPCMP0 AMP0TS2 AMP0TS1 AMP0TS0
AMP0CSR
AMP1+
AMP1-
+
Toward ADC MUX
(AMP1)
-
ADCK/8
00
01
10
Timer 0 Compare Match
Timer 0 Overflow
Timer 1 Compare Match
Timer 1 Overflow
PSS0
Amplifier 1
Clock
01
PSS1
PSS2
AMP1EN AMP1IS AMP1G1 AMP1G0 AMPCMP1 AMP1TS2 AMP1TS1 AMP1TS0
AMP1CSR
AMP2+
AMP2-
+
Toward ADC MUX
(AMP2)
-
ADCK/8
00
01
10
Timer 0 Compare Match
Timer 0 Overflow
Timer 1 Compare Match
Timer 1 Overflow
PSS0
Amplifier 2
Clock
01
PSS1
PSS2
AMP2EN AMP2IS AMP2G1 AMP2G0 AMPCMP2 AMP2TS2 AMP2TS1 AMP2TS0
AMP2CSR
ATmega16/32/64/M1/C1 [DATASHEET]
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