Table 18-9. AMP0 Clock Source Selection
AMP0TS2
AMP0TS1
AMP0TS0
Clock Source
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ADC clock/8
Timer/Counter0 compare match
Timer/Counter0 overflow
Timer/Counter1 compare match B
Timer/Counter1 overflow
PSC module 0 synchronization signal (PSS0)
PSC module 1 synchronization signal (PSS1)
PSC module 2 synchronization signal (PSS2)
18.11.2 Amplifier 1 Control and Status Register – AMP1CSR
Bit
7
6
5
4
3
2
1
0
AMP1EN AMP1IS AMP1G1 AMP1G0 AMPCMP1 AMP1TS2 AMP1TS1 AMP1TS0 AMP1CSR
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 7 – AMP1EN: Amplifier 1 Enable Bit
Set this bit to enable the Amplifier 1.
Clear this bit to disable the Amplifier 1.
Clearing this bit while a conversion is running will take effect at the end of the conversion.
Warning: Always clear AMP1TS0:1 when clearing AMP1EN.
• Bit 6 – AMP1IS: Amplifier 1 Input Shunt
Set this bit to short-circuit the Amplifier 1 input.
Clear this bit to normally use the Amplifier 1.
• Bit 5, 4 – AMP1G1, 0: Amplifier 1 Gain Selection Bits
These 2 bits determine the gain of the amplifier 1.
The different setting are shown in Table 18-10.
Table 18-10. Amplifier 1 Gain Selection
AMP1G1
AMP1G0
Description
Gain 5
0
0
1
1
0
1
0
1
Gain 10
Gain 20
Gain 40
To ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite stable input
value during at least 4 Amplifier synchronization clock periods.
• Bit 3 – AMPCMP1: Amplifier 1 - Comparator 1 connection
Set this bit to connect the amplifier 1 to the comparator 1 positive input. In this configuration the comparator clock is twice
amplifier clock. Clear this bit to normally use the Amplifier 1.
• Bit 2:0 – AMP1TS2,AMP1TS1, AMP1TS0: Amplifier 1 Clock Source Selection Bits
In accordance with the Table 18-11, these 3 bits select the event which will generate the clock for the amplifier 1. This clock
source is necessary to start the conversion on the amplified channel.
ATmega16/32/64/M1/C1 [DATASHEET]
219
7647O–AVR–01/15