Table 18-7. ADC Auto Trigger Source Selection
ADTS3
ADTS2
ADTS1
ADTS0
Description
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Free running mode
External interrupt request 0
Timer/Counter0 compare match
Timer/Counter0 overflow
Timer/Counter1 compare match B
Timer/Counter1 overflow
Timer/Counter1 capture event
PSC Module 0 synchronization signal
PSC Module 1 synchronization signal
PSC Module 2 synchronization signal
Analog comparator 0
Analog comparator 1
Analog comparator 2
Analog comparator 3
Reserved
Reserved
18.9.4 ADC Result Data Registers – ADCH and ADCL
When an ADC conversion is complete, the conversion results are stored in these two result data registers.
When the ADCL register is read, the two ADC result data registers can’t be updated until the ADCH register has also been
read.
Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH.
Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the result thanks to the ADLAR bit
in the ADCSRA register. Like this, it is sufficient to only read ADCH to have the conversion result.
18.9.4.1 ADLAR = 0
Bit
7
6
5
4
3
2
1
0
-
-
-
-
-
-
ADC9
ADC8
ADCH
ADCL
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
Read/Write
Initial Value
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
0
0
0
0
0
0
0
0
18.9.4.2 ADLAR = 1
Bit
7
6
5
4
3
2
1
0
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADCL
ADC1
ADC0
-
-
-
-
-
-
Read/Write
Initial Value
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
0
0
0
0
0
0
0
0
ATmega16/32/64/M1/C1 [DATASHEET]
213
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
