18.9.5 Digital Input Disable Register 0 – DIDR0
Bit
7
6
5
4
3
2
1
0
ADC6D
ADC7D ACMPN1D
AMP2ND
ADC5D
ACMPN0D
ADC3D
ACMPN2D ACMP2D
ADC2D
ADC0D
ACMPN3D
ADC4D
ADC1D
DIDR0
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 7:0 – ADC7D..ADC0D, ACMPN0D, ACMPN1D, ACMPN2D, ACMPN3D, ACMP2D, AMP2ND:
ADC7:0, ACMPN0, ACMPN1, ACMPN2, ACMPN3, ACMP2, AMP2N Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN
register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital
input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
18.9.6 Digital Input Disable Register 1– DIDR1
Bit
7
6
5
4
3
2
1
0
ADC9D
AMP1PD
ACMP3D
ADC10D
ACMP1D
ADC8D
AMP1ND
-
AMP2PD ACMP0D AMP0PD AMP0ND
DIDR1
Read/Write
Initial Value
-
-
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
• Bit 6:0 – ADC10D..8D, ACMP0D, ACMP1D, ACMP3D, AMP0PD, AMP0ND, AMP1PD, AMP1ND, AMP2PD:
ADC10..8, ACMP0, ACMP1, ACMP3, AMP0P, AMP0N, AMP1P, AMP1N, AMP2P Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN
register bit will always read as zero when this bit is set. When an analog signal is applied to an analog pin and the digital
input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
18.10 Amplifier
The ATmega16/32/64/M1/C1 features three differential amplified channels with programmable 5, 10, 20, and 40 gain stage.
Because the amplifiers are switching capacitor amplifiers, they need to be clocked by a synchronization signal called in this
document the amplifier synchronization clock. To ensure an accurate result, the amplifier input needs to have a quite stable
input value during at least 4 Amplifier synchronization clock periods. The amplifiers can run with a clock frequency of up to
250kHz (typical value).
To ensure an accurate result, the amplifier input needs to have a quite stable input value at the sampling point during at least
4 amplifier synchronization clock periods.
Amplified conversions can be synchronized to PSC events (See Section 14-8 “Synchronization Source Description in One
Ramp Mode” on page 128 and Section 14-9 “Synchronization Source Description in Centered Mode” on page 129) or to the
internal clock CKADC equal to eighth the ADC clock frequency. In case the synchronization is done the ADC clock divided by
8, this synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a
specific phase of CKADC2. A conversion initiated by the user (i.e., all single conversions, and the first free running conversion)
when CKADC2 is low will take the same amount of time as a single ended conversion (13 ADC clock cycles from the next
prescaled clock cycle). A conversion initiated by the user when CKADC2 is high will take 14 ADC clock cycles due to the
synchronization mechanism.
The normal way to use the amplifier is to select a synchronization clock via the AMPxTS1:0 bits in the AMPxCSR register.
Then the amplifier can be switched on, and the amplification is done on each synchronization event.
In order to start an amplified analog to digital conversion on the amplified channel, the ADMUX must be configured as
specified on Table 18-5 on page 211.
The ADC starting requirement is done by setting the ADSC bit of the ADCSRA register.
Until the conversion is not achieved, it is not possible to start a conversion on another channel.
In order to have a better understanding of the functioning of the amplifier synchronization, two timing diagram examples are
shown in Figure 18-15 on page 215 and Figure 18-16 on page 216.
214
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
