As soon as a conversion is requested thanks to the ADSC bit, the analog to digital conversion is started. In case the amplifier
output is modified during the sample phase of the ADC, the on-going conversion is aborted and restarted as soon as the
output of the amplifier is stable. This ensure a fast response time. The only precaution to take is to be sure that the trig signal
(PSC) frequency is lower than ADCclk/4.
Figure 18-15. Amplifier Synchronization Timing Diagram with Change on Analog Input Signal
Delta V
4th stable sample
Signal to be
measured
PSC
Block
PSCn_ASY
AMPLI_clk
(Sync Clock
CK ADC
Amplifier
Block
Amplifier Sample
Enable
Amplifier Hold
Value
Valid sample
ADSC
ADC
ADC
Activity
ADC
Conv
ADC
Conv
ADC
Sampling
ADC
Sampling
ADC Result
Ready
ADC Result
Ready
ATmega16/32/64/M1/C1 [DATASHEET]
215
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
