Table 18-5. ADC Input Channel Selection
MUX4
MUX3
MUX2
MUX1
MUX0
Description
ADC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
Temp sensor
VCC/4
ISRC
AMP0
AMP1 (– is ADC8, + is ADC9)
AMP2 (– is ADC6)
Bandgap
GND
Reserved
Reserved
Reserved
x
x
If these bits are changed during a conversion, the change will not take effect until this conversion is complete (it means while
the ADIF bit in ADCSRA register is set).
18.9.2 ADC control and status register A – ADCSRA
Bit
7
ADEN
R/W
0
6
ADSC
R/W
0
5
ADATE
R/W
0
4
ADIF
R/W
0
3
ADIE
R/W
0
2
ADPS2
R/W
0
1
ADPS1
R/W
0
0
ADPS0 ADCSRA
Read/Write
Initial Value
R/W
0
• Bit 7 – ADEN: ADC Enable Bit
Set this bit to enable the ADC.
Clear this bit to disable the ADC.
Clearing this bit while a conversion is running will take effect at the end of the conversion.
• Bit 6– ADSC: ADC Start Conversion Bit
Set this bit to start a conversion in single conversion mode or to start the first conversion in free running mode.
Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect.
The first conversion performs the initialization of the ADC.
• Bit 5 – ADATE: ADC Auto trigger Enable Bit
Set this bit to enable the auto triggering mode of the ADC.
Clear it to return in single conversion mode.
In auto trigger mode the trigger source is selected by the ADTS bits in the ADCSRB register. See Table 18-7 on page 213.
ATmega16/32/64/M1/C1 [DATASHEET]
211
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
