Table 14-9. Synchronization Source Description in Centered Mode
PSYNCn1
PSYNCn0
Description
Send signal on match with OCRnRA (during counting down of PSC). The min value of
OCRnRA must be 1.
0
0
Send signal on match with OCRnRA (during counting up of PSC). The min value of
OCRnRA must be 1.
0
1
1
1
0
1
no synchronization signal
no synchronization signal
14.16.3 PSC Output Compare SA Register – POCRnSAH and POCRnSAL
Bit
7
6
5
4
3
2
1
0
–
–
–
–
POCRnSA[11:8]
POCRnSAH
POCRnSAL
POCRnSA[7:0]
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14.16.4 PSC Output Compare RA Register – POCRnRAH and POCRnRAL
Bit
7
6
5
4
3
2
1
0
–
–
–
–
POCRnRA[11:8]
POCRnRAH
POCRnRAL
POCRnRA[7:0]
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14.16.5 PSCOutput Compare SB Register – POCRnSBH and POCRnSBL
Bit
7
6
5
4
3
2
1
0
–
–
–
–
POCRnSB[11:8]
POCRnSBH
OCRnSBL
POCRnSB[7:0]
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14.16.6 PSC Output Compare RB Register – POCR_RBH and POCR_RBL
Bit
7
6
5
4
3
2
1
0
–
–
–
–
POCRnRB[11:8]
POCR_RBH
POCR_RBL
POCRnRB[7:0]
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Note:
n = 0 to 2 according to module number.
The output compare registers RA, RB, SA and SB contain a 12-bit value that is continuously compared with the PSC counter
value. A match can be used to generate an output compare interrupt, or to generate a waveform output on the associated
pin.
The output compare registers are 16bit and 12-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers.
ATmega16/32/64/M1/C1 [DATASHEET]
129
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
