15. Serial Peripheral Interface – SPI
The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the ATmega16/32/64/M1/C1 and
peripheral devices or between several AVR devices.
The ATmega16/32/64/M1/C1 SPI includes the following features:
15.1 Features
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Full-duplex, three-wire synchronous data transfer
Master or slave operation
LSB first or MSB first data transfer
Seven programmable bit rates
End of transmission interrupt flag
Write collision flag protection
Wake-up from idle mode
Double speed (CK/2) master SPI mode
Figure 15-1. SPI Block Diagram(1)
SPIPS
MISO
MISO
_A
S
M
M
MSB
8 Bit Shift Register
Read Data Buffer
LSB
MOSI
CLKI/O
S
MOSI
_A
Divider
2/4/8/16/32/66/128
SCK
Clock
SCK
_A
SPI Clock (Master)
S
Clock
Logic
Select
M
SS
SS_A
MSTR
SPE
SPI Control
8
SPI Status Register
SPI Control Register
8
8
SPI Interrupt
Request
Internal
Data Bus
Note:
1. Refer to Figure 1-1 on page 3, and Table 9-3 on page 58 for SPI pin placement.
ATmega16/32/64/M1/C1 [DATASHEET]
133
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
