14.16.7 PSC Configuration Register – PCNF
Bit
7
-
6
-
5
4
3
POPB
R/W
0
2
POPA
R/W
0
1
-
0
-
PULOCK PMODE
PCNF
Read/Write
Initial Value
R
0
R
0
R/W
0
R/W
0
R
0
R
0
• Bit 7:6 - not use
not use
• Bit 5 – PULOCK: PSC Update Lock
When this bit is set, the output compare registers POCRnRA, POCRnSA, POCRnSB, POCR_RB and the PSC output
configuration registers POC can be written without disturbing the PSC cycles. The update of the PSC internal registers will
be done if the PULOCK bit is released to zero.
• Bit 4 – PMODE PSC Mode
Select the mode of PSC.
Table 14-10. PSC Mode Selection
PMODE
Description
0
1
One ramp mode (edge aligned)
Center aligned mode
• Bit 3 – POPB: PSC B Output Polarity
If this bit is cleared, the PSC outputs B are active low.
If this bit is set, the PSC outputs B are active high.
• Bit 2 – POPA: PSC A Output Polarity
If this bit is cleared, the PSC outputs A are active low.
If this bit is set, the PSC outputs A are active high.
• Bit 1:0 – not use
not use
14.16.8 PSC Control Register – PCTL
Bit
7
PPRE1
R/W
0
6
5
4
3
2
1
0
PRUN
R/W
0
PPRE0 PCLKSEL SWAP2 SWAP1 SWAP0 PCCYC
PCTL
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 7:6 – PPRE1:0 : PSC Prescaler Select
This two bits select the PSC input clock division factor. All generated waveform will be modified by this factor.
Table 14-11. PSC Prescaler Selection
PPRE1
PPRE0
Description
0
0
1
1
0
1
0
1
No divider on PSC input clock
Divide the PSC input clock by 4
Divide the PSC input clock by 32
Divide the PSC clock by 256
• Bit 5 – PCLKSEL: PSC Input Clock Select
This bit is used to select between CLKPLL or CLKIO clocks.
Set this bit to select the fast clock input (CLKPLL). Clear this bit to select the slow clock input (CLKIO).
130
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
