Table 14-6. Output Clock versus Selection and Prescaler
PCLKSELn
PPREn1
PPREn0
CLKPSCn output
CLK I/O
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CLK I/O / 4
CLK I/O / 32
CLK I/O / 256
CLK PLL
CLK PLL / 4
CLK PLL / 32
CLK PLL / 256
14.15 Interrupts
This section describes the specifics of the interrupt handling as performed in ATmega16/32/64/M1/C1.
14.15.1 Interrupt Vector
PSC provides 2 interrupt vectors:
●
●
PSC_End (end of cycle): When enabled and when a match with POCR_RB occurs
PSC_Fault (fault event): When enabled and when a PSC input detects a fault event.
14.15.2 PSC Interrupt Vectors in ATmega16/32/64/M1/C1
Table 14-7. PSC Interrupt Vectors
Vector
No.
Program
Address
Source
Interrupt Definition
-
5
6
-
-
-
-
-
0x0004
PSC_Fault
PSC_End
-
PSC fault event
0x0005
PSC end of cycle
-
-
-
-
-
14.16 PSC Register Definition
Registers are explained for PSC module 0. They are identical for module 1 and module 2.
14.16.1 PSC Output Configuration – POC
Bit
7
-
6
-
5
4
3
2
1
0
POEN2B POEN2A POEN1B POEN1A POEN0B POEN0A
POC
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 7 – not use
not use
• Bit 6 – not use
not use
• Bit 5 – POEN2B: PSC Output 2B Enable
When this bit is clear, I/O pin affected to PSCOUT2B acts as a standard port.When this bit is set, I/O pin affected to
PSCOUT2B is connected to the PSC module 2 waveform generator B output and is set and clear according to the PSC
operation.
ATmega16/32/64/M1/C1 [DATASHEET]
127
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
