14.9.1.2 Signal Polarity
One can select the active edge (edge modes) or the active level (level modes). See PELEVnx bit description in Section
14.16.9 “PSC Module n Input Control Register – PMICn” on page 131.
If PELEVnx bit set, the significant edge of PSCn Input A or B is rising (edge modes) or the active level is high (level modes)
and vice versa for unset/falling/low
●
In 2- or 4-ramp mode, PSCn Input A is taken into account only during Dead-Time0 and On-Time0 period (respectively
Dead-Time1 and On-Time1 for PSCn input B).
●
In 1-ramp-mode PSC Input A or PSC Input B act on the whole ramp.
14.9.1.3 Input Mode Operation
Thanks to 4 configuration bits (PRFM3:0), it’s possible to define the mode of the PSC inputs.
Table 14-5. PSC Input Mode Operation
PRFMn2:0
000b
Description
No action, PSC input is ignored
001b
Disactivate module n outputs A
010b
Disactivate module n output B
011b
Disactivate module n output A and B
Disactivate all PSC output
10x
11xb
Halt PSC and wait for software action
All following examples are given with rising edge or high level active inputs.
Note:
14.10 PSC Input Modes 001b to 10xb: Deactivate Outputs without Changing Timing
Figure 14-12. PSC Behavior versus PSCn Input in Mode 001b to 10xb
DT0 OT0 DT1
OT1
DT0 OT0
DT1
OT1
DT0 OT0 DT1 OT1
PSCOUTnA
PSCOUTnB
PSC Input
Figure 14-13. PSC Behavior versus PSCn Input A or Input B in Fault Mode 4
DT0 OT0 DT1
OT1
DT0 OT0
DT1
OT1 DT0 OT0
DT1 OT1
PSCOUTnA
PSCOUTnB
PSC Input
PSCn Input acts indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
ATmega16/32/64/M1/C1 [DATASHEET]
125
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
