14.11 PSC Input Mode 11xb: Halt PSC and Wait for Software Action
Figure 14-14. PSC Behavior versus PSCn Input A in Fault Mode 11xb
DT0 OT0 DT1 OT1
DT0 OT0
DT0 OT0
DT1 OT1
PSCOUTnA
PSCOUTnB
PSC Input
Software Action (1)
Note:
Software action is the setting of the PRUNn bit in PCTLn register.
Used in fault mode 7, PSCn input A or PSCn input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-
Time1.
14.12 Analog Synchronization
Each PSC module generates a signal to synchronize the ADC sample and hold; synchronisation is mandatory for
measurements.
This signal can be selected between all falling or rising edge of PSCOUTnA or PSCOUTnB outputs.
In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchronization of the ADC. It this case,
it’s minimum value is 1.
14.13 Interrupt Handling
As each PSC module can be dedicated for one function, each PSC has its own interrupt system (vector .. )
List of interrupt sources:
●
●
●
Counter reload (end of on time 1)
PSC input event (active edge or at the beginning of level configured event)
PSC mutual synchronization error
14.14 PSC Clock Sources
Each PSC has two clock inputs:
●
●
CLK PLL from the PLL
CLK I/O
Figure 14-15. Clock Selection
CLK
1
0
PLL
CK
Prescaler
CLK
I/O
PCLKSEL
PPREn1/0
CLK
PSCn
PCLKSELn bit in PSC control register (PCTL) is used to select the clock source.
PPREn1/0 bits in PSC control register (PCTL) are used to select the divide factor of the clock.
126
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
