AT25128B/AT25256B
Write Sequence
8.
Write Sequence
In order to program the AT25128B/AT25256B, two separate instructions must be executed. First, the
device must be write enabled via the Write Enable (WREN) instruction. Then, one of the two possible write
sequences described in this section may be executed.
Note:ꢀ If the device is not Write Enabled (WREN), the device will ignore the WRITEinstruction and will
return to the standby state when CS is brought high. A new CS assertion is required to re‑initiate
communication.
The address of the memory location(s) to be programmed must be outside the protected address field
location selected by the block write protection level. During an internal write cycle, all commands will be
ignored except the RDSRinstruction. Refer to Table 8-1 for the address bits for AT25128B/AT25256B.
Table 8-1.ꢀAT25128B/AT25256B Address Bits
Address
AN
AT25128B
A13–A0
AT25256B
A14–A0
A15
Don’t Care Bits
A15–A14
8.1
Byte Write
A Byte Write requires the following sequence and is depicted in Figure 8-1. After the CS line is pulled low
to select the device, the WRITE(02h) instruction is transmitted via the SI line followed by the 16‑bit
address and the data (D7‑D0) to be programmed. Programming will start after the CS pin is brought high.
The low‑to‑high transition of the CS pin must occur during the SCK low time (Mode 0) and SCK high time
(Mode 3) immediately after clocking in the D0 (LSB) data bit. The AT25128B/AT25256B is automatically
returned to the Write Disable state (STATUS register bit WEL = 0) at the completion of a write cycle.
Figure 8-1.ꢀByte Write
CS
(1)
tWC
0
1
2
3
4
5
6
7
8
9
10 11 12
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
WRITE Opcode (02h)
Address Bits A15-A0
Data In
0
0
0
0
0
0
1
0
A
A
A
A
A
A
A
A
A
D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
MSB
High-Impedance
SO
Note:ꢀ
1. This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.
DS20006193A-page 24
© 2019 Microchip Technology Inc.
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