AT25128B/AT25256B
Write Sequence
8.2
Page Write
A Page Write sequence allows up to 64 bytes to be written in the same write cycle, provided that all bytes
are in the same row of the memory array. Partial Page Writes of less than 64 bytes are allowed. After
each byte of data is received, the six lowest order address bits are internally incremented following the
receipt of each data byte. The higher order address bits are not incremented and retain the memory array
page location. If more bytes of data are transmitted that what will fit to the end of that memory row, the
address counter will rollover to the beginning of the same row. Nevertheless, creating a rollover event
should be avoided as previously loaded data in the page could become unintentionally altered. The
AT25128B/AT25256B is automatically returned to the Write Disable state (WEL = 0) at the completion of
a write cycle.
Figure 8-2.ꢀPage Write
CS
(1)
tWC
0
1
2
3
4
5
6
7
8
9
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
WRITE Opcode (02h)
Address Bits A15-A0
Data In Byte 1
Data In Byte 64
0
0
0
0
0
0
1
0
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
MSB
MSB
MSB
MSB
High-Impedance
SO
Note:ꢀ
1. This instruction initiates a self‑timed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.
8.3
Polling Routine
A polling routine can be implemented to optimize time‑sensitive applications that would not prefer to wait
the fixed maximum write cycle time (tWC). This method allows the application to know immediately when
the write cycle has completed to start a subsequent operation.
Once the internally-timed write cycle has started, a polling routine can be initiated. This involves
repeatedly sending Read STATUS Register (RDSR) instruction to determine if the device has completed
its self-timed internal write cycle. If the RDY/BSY bit (bit 0 of STATUS register) = 1, the write cycle is still
in progress. If bit 0 = 0, the write cycle has ended. If the RDY/BSY bit = 1, repeated RDSRcommands can
be executed until the RDY/BSY bit = 0, signaling that the device is ready to execute a new instruction.
Only the Read STATUS Register (RDSR) instruction is enabled during the write cycle.
DS20006193A-page 25
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